The present invention relates to an improved low temperature capacitor attachment method for circuit carriers using flip chip attach (FCA) technology. More particularly, the invention relates to a structure where at least one multi-dielectric layered capacitor can be directly attached to a substrate using multilevel interconnection technology. A method for such direct capacitor attachment to a card is also disclosed.
Electronic products are typically comprised of a plurality of electrical components. Examples of electrical components include, but are not limited to, logic chips, memory chips, register chips, resistors, capacitors, to name a few.
At least three hierarchial levels of assembly are usually necessary in the production of electronic products for high-end computer CPUs where performance of complex functions is necessary.
At the first level of the hierarchical assembly the components are usually connected to carriers made of ceramic or organic laminates and the assembled carriers, along with sealing and cooling methodologies known in the art, are called modules.
There are a number of types of carriers commonly known in the art including, ceramic and organic laminates. Generally, ceramic carriers are made of alumina or glass. Ceramics are robust but tend to be high cost. There are two types of organic laminates, one type is generally made of epoxy compounds and is generally thick and stiff. The other type of organic laminate is made of polyimide and is flexible. The carriers generally contain at least one layer of metal interconnection lines.
At the second level of the assembly hierarchy, the modules are connected to cards. The cards are usually made of organic laminates with printed circuits on at least one side of the card.
At the third level of the assembly hierarchy the cards are connected to boards.
The capacitors typically used in the electronic circuits generally have negligibly small inductance. Historically, this has been true because the back voltage produced by a sudden flow of current due to the simultaneous switching of several circuits is detrimental. The back voltage must therefore be minimized at every possible point. However, the methods used for electrically and mechanically attaching discrete capacitors to circuit carrier cards tend to lead to high inductance capacitors. There are a number of attachment methods used in the industry.
One attachment method which is the wire bond technique has historically imposed high inductances because current has to travel along the length of the wire.
Another attachment method which is TAB (tape-automated-bonding) is mostly used for attaching integrated circuit chips. It has been found that TAB will also further increase the inductance in capacitors.
A third attachment method which is using the C4 (Controlled Collapse Chip Connection) technology. The C4 attachment method, has been successfully employed for first level assembly of chips. The C4 interconnection is basically comprised of two main elements, a solder wettable pad called ball limiting metallurgy (BLM), and a ball of solder. The BLM is usually comprised of an adhesive layer, such as, Cr or TiW, and a solder reflowable layer, such as, copper or nickel. The BLM materials and their thicknesses are judiciously chosen to provide reliable electrical, mechanical and thermal stability for the interconnect structures. The solder material used for C4 is preferably a low percentage tin/lead alloy. The lead/tin alloy is typically used to reduce the reaction between the copper in the BLM and the tin, because copper-tin intermetallics form a high stress film which cracks the polyimide, a passivation on the chip. Additionally the alloy is used to achieve more desirable thermal fatigue characteristics.
Ceramic substrates are undesirable because they are less compatible with present design considerations. For example, product miniaturization, especially in some microprocessing areas, cost reduction and low inductance requirements make it difficult to effectively use ceramic substrates for packaging. Presently, there are concerns that limit the use of current C4 technology for direct chip attachment (DCA) on carrier cards. The foremost problem is the relatively high joining temperature (between about 340xc2x0 C. to about 380xc2x0 C.) for standard C4s. The joining temperature being higher than the phase transition temperature of the organics used in the card thus precludes the use of organic card materials.
There are generally two ways to lower the DCA joining temperature, and both ways would alleviate the problem cited above. Either the substrate can be modified or treated to achieve the desired results, or the solder ball can be modified or treated to achieve the desired results.
A number of approaches treat or modify the substrate. The general scheme for attaching IC chips to organic circuit carrier cards having C4s involves a xe2x80x9ctinnedxe2x80x9d substrate. The xe2x80x9ctinnedxe2x80x9d substrate consists of a standard substrate treated with an alloy of eutectic composition in the contact regions, also called pre-coating. The precoated substrate is then interacted with the standard C4 solder balls on the base of the chip.
A second approach for lowering the joining temperature for Direct Chip Attach (DCA), is to provide a low melting solder-on-chip (SOC) C4. In one method, an eutectic alloy is formed from a sufficiently thick, heterogeneous anisotropic column consisting of a lead rich bottom and a tin rich top. The resulting unreflowed column is then joined onto the card""s conductor. In such heterogeneous schemes, the tin rich top material reacts with the lead rich bottom material to form an eutectic alloy. However, the eutectic composition is only transient because lead and tin rapidly interdiffuse to form a solder alloy with a tin content which is less than that of the eutectic alloy. The resulting alloy has a melting point which is higher than the required eutectic temperature and forms a poor joint. Further, the problem of BLM degradation, due to a higher tin content remains.
One method to circumvent the thermodynamically driven tendency for interdiffusion involves a structure where the low melting point component is separated from the high melt component by a barrier metal layer. This structure does show a hierarchy of solder material. However, in this structure the columns of high melting solder are generally not reflowed. Since the stacked solder are not reflowed, there is no metallurgical reaction between the solder stack and the adhesive pad of BLM. Poor mechanical integrity of the C4 joint is known to exist if there is no metallurgical reaction between the solder stack and the adhesive pad of the BLM.
Another method involves the use of a heterogeneous solder stack of Tin-Lead-Tin. In this method, the bottom layer of tin is utilized to make an intermetallic compound with the copper in the BLM. The intermetallic compound adds mechanical strength. A top layer of tin alloys with the underlying lead. The top tin/lead alloy provides a localized eutectic formation, but only as a transient state. The transitory liquid phase formation is one aspect of reflow joining that must be avoided as it tends to result in a poor chip joining yield.
The manufacturability aspects of chip joining become even more sensitive if the heterogeneous solder stack is composed of metals with thermodynamic potential for intermetallic compound formation, e.g., gold-tin metallurgy for TAB. In such cases, one has to be careful to heat only the tin portion of the heterogeneous stack.
For the purposes of this invention a solder ball composed completely of a low melting point composition is undesirable because the high tin content reacts with the copper of the adhesive layer (BLM) resulting in a thick intermetallic layer. High stresses in reacted BLM have been known to cause solder pad failure and delamination and also result in insulation cracking. Additionally, eutectic solder bumps composed entirely of low melting point metals tend to have poor electromigration and shorter thermal fatigue lifetimes. It is also known that low melting eutectic solder can increase void formation due to thermal migration. Void formation and thermal migration can cause circuit failure.
Yet another drawback of a heterogeneous, anisotropic solder column is that this structure is not conducive to electrical testing of circuitry. It is desirable to test circuitry before joining the chips to carriers as the electrical probes can gouge into a low melting point covering during testing and degrade the integrity of the solder ball.
Thus, there remains a need for a method for attaching a capacitor, having a plurality of electrodes to a card. One way this can be achieved is by providing a solder assembly where a high melting point solder is covered on the top surface with a low melting point metal. And, upon subsequent reflow the low melting point metal forms an eutectic solder with at least a portion of the high melting point solder.
It is therefore a purpose of the present invention to provide a method and structure for providing direct device attachment to organic circuit cards.
It is another purpose of the present invention to provide a method for preparing capacitors for direct device attachment.
It is yet another purpose of this invention to provide a method for simultaneously joining devices on card using the direct chip attachment, and other technologies.
It is a further purpose of this invention to provide a circuit card/capacitor assembly which has increased performance.
It is still another purpose of this invention to have a capacitor/carrier card assembly which is compatible with electrical test and burn-in protocols.
Thus, in one aspect the present invention comprises a process of forming a capacitor with at least one low melting point metallic cap, comprising:
(a) securing at least one high melting point solder ball to said capacitor, such that said solder ball is in electrical communication with said capacitor,
(b) positioning a mask having at least one opening over said solder ball, such that at least a portion of said opening in said mask accommodates and exposes at least a portion of said solder ball,
(c) depositing at least one layer of at least one low melting point metal through said opening in said mask over said exposed surface of said solder ball, and thereby forming said capacitor with said at least one low melting point metallic cap.
In another aspect the present invention comprises an organic package comprising, a device carrier and at least one capacitor electrically connected to said device carrier with at least one solder ball, wherein said solder ball comprises a high melting point solder in communication with an electrical feature on said capacitor, a portion of said solder ball having a coating of at least one low melting point metal, and wherein a portion of said low melting point metal forms an eutectic fillet, and wherein said eutectic fillet is in electrical contact with said device carrier and thereby forms said organic package.